FIGS. 1A–1I show the process of forming a gate alignment mark in the fabrication process of a conventional ultrafine semiconductor device.
Referring to FIG. 1A, the ultrafine semiconductor device is formed on an SOI substrate 10 in which an SiO2 buried insulation layer 11B having a thickness of typically 400 nm and a single crystal Si active layer 11C having a thickness of typically 500 nm are formed consecutively on a support substrate 11A of Si, and the like. Thereby, formation of the gate alignment mark is conducted simultaneously to the formation of the device isolation structure of the STI (shallow trench isolation) structure.
More specifically, a device array region 10A, in which the STI device isolation structure is formed, and an alignment mark forming region 10B, in which the gate alignment marks are formed, are defined on the SOI substrate 10 in the process of FIG. 1A. The device array region 10A and the alignment mark forming region 10B are covered by an SiO2 film 12 having a thickness of about 10 nm and an SiN film 13 having a thickness of about 110 nm. For example, the SiO2 film 12 may be formed by a hydrochloric acid oxidation process conducted at 900° C. On the other hand, a CVD process is used to form the SiN film 13.
Next, a resist pattern 14 shown in FIG. 1C is formed on the structure of FIG. 1A in the process of FIG. 1B, and the SiN film 13 and the SiO2 film 12 underneath the SiN film 13 are patterned while using the resist pattern 14 as a mask. With this, SiO2 patterns 12A and SiN patterns 13A are formed on the Si active layer 11C as shown in FIG. 1C. Referring to FIGS. 1B and 1C, the SiN pattern 13A includes patterns 13a that cover the device region of the semiconductor device in the device array region 10A. Further, the SiN pattern 13A includes mask openings 13b and 13c corresponding to the alignment marks to be formed in the alignment mark formation region 10B. The mask openings 13b and 13c are formed in correspondence to the resist openings 14A and 14B of the resist pattern 14.
Thus, in the step of FIG. 1D, device isolation grooves 11a are formed in the active layer 11C in correspondence to the device array region 10A by patterning the Si active layer 11C by a dry etching process while using the SiN pattern 13A as a hard mask. Simultaneously, alignment marks 11b are formed in the active layer 11C of the alignment mark formation region 10B in the form of grooves. It should be noted that the dry etching process is conducted, when forming the device isolation grooves 11a and the alignment marks 11b, until the buried SiO2 insulation film 11B is exposed. As a result of the patterning process, there are formed device regions 11c of Si in the device array region 10A between a device isolation groove 11a and a next device isolation groove 11a. In the alignment mark formation region 10B, on the other hand, Si regions 11d are formed between a pair of mutually adjacent grooves. It should be noted that the Si region 11d forms the alignment mark together with the grooves 11b. 
Next, in the step of FIG. 1E, an SiO2 film 15 is deposited on the structure of FIG. 1D by a CVD process such that the SiO2 film 15 covers the device region 11c or the Si region 11d with a thickness of about 700 nm. Further, in the step of FIG. 1F, the SiO2 film 15 is polished by a CMP process while using the SiN pattern 13A as a polishing stopper. Further, in the step of FIG. 1G, the SiN pattern 13A and also the SiO2 pattern 12A underneath the SiN pattern 13A are removed respectively by using a pyrolytic phosphoric acid and an HF etchant. In the step of FIG. 1E, the SiO2 film 15 fills the grooves 11a and 11b, and as a result, there are formed device isolation insulation film patterns 15A in the step of FIG. 1G in the device array region 10A in correspondence to the device isolation grooves 11a. Thereby, it should be noted that a device region 11c is formed between a pair of neighboring device isolation film patterns 15A. Also, in the alignment mark formation region 10B, the SiO2 patterns 15B are formed in correspondence to the grooves 11b, such that SiO2 patterns sandwich the Si pattern 11d laterally.
Next, in the step of FIG. 1H, a resist pattern 16 exposing the alignment mark formation region 10B of FIG. 1I is formed such that the resist pattern 16 covers the structure of FIG. 1G, and the SiO2 pattern 15B is removed in the alignment mark formation region 10B by a dry etching process that uses a CHF3/CF4 mixed gas as an etching gas for example, while using the resist pattern 16 as a mask. By removing the resist pattern 16, a structure in which the device regions 11c are separated from each other by the device isolation regions 15A, is formed in the device array region 10A. Also, an alignment mark having a planar form explained previously with reference to FIG. 1C is formed in the alignment mark formation region 10B such that the alignment mark is formed of the Si patterns 11d and the grooves lie formed adjacent to the Si patterns 11d in correspondence to the SiO2 patterns 15B. It should be noted that FIG. 1H is a cross-sectional diagram taken along a line x–x′ of FIG. 1I.
In such a semiconductor device of the conventional construction, it should be noted that the gate electrode pattern is formed on the device region 11c in the array region 10A by using a ultra high resolution exposure method including an electron beam exposure method as explained previously. Thereby, a Si pattern 11d in the alignment mark formation region 10B is used as an alignment mark, and alignment of the exposure apparatus is achieved by detecting the step height associated with the Si pattern 11d. According to the conventional construction noted above, the formation of the alignment mark and the formation of the device isolation region are conducted simultaneously by using the same mask. Because of this, it is possible to form the gate electrode with high precision.
On the other hand, it is required that the Si pattern 11d forms a sufficiently large step height in order that the alignment mark can be detected by an ultra high resolution exposure apparatus. In the case of using an electron beam exposure apparatus, it is necessary that a step height of at least 500 nm is formed. Because of this, it has been conventionally practiced to set the thickness of the Si layer 11C to about 700 nm as explained previously.
On the other hand, with further advance of miniaturization in such conventional semiconductor devices, it will be noted that the pitch of the openings in the resist pattern 14 used in the process of FIG. 1B is reduced particularly in the device array region 10A, and as a result, the interval between the SiN patterns 13a in FIG. 1C, and hence the interval between the Si device regions 11c in FIG. 1D, is reduced. However, the aspect ratio of the device isolation groove 11a formed between the Si device regions 11c is inevitably increased in such a miniaturized structure, when an attempt is made to secure a step height of about 500 nm for the Si pattern 11d in the alignment mark formation region 10B. When this is the case, there may be a problem that the deposited CVD layer 15 cannot fill the groove 11a completely in the step of FIG. 1E and a void may be formed inside. As such a void can induce various levels on the surface thereof, there can be a case in which the device isolation structure cannot provide the desired device isolation performance especially in the case the device is miniaturized further. For example, the aspect ratio of 1 in the structure of FIG. 1D for the case in which the width of the device isolation groove 11a is set to 0.5 μm, increases to the value of 2.5 when the width of the groove 11a is reduced to 0.2 μm.
In order to resolve this problem, it is necessary to reduce the thickness of the Si active layer 11C. In such a case, however, the step height of the Si pattern 11d forming the alignment mark is reduced correspondingly, and as a result, the necessary alignment cannot be achieved when the substrate is loaded in an electron beam exposure apparatus.
In view of this situation note above, it may be conceivable to use a mask different from the one used for forming the grooves 11b in the alignment mark formation region 10B, for forming the device isolation groove 11a in the device array region 10A, in the approach of decreasing the thickness of the Si active layer 11C. In this case, the device isolation grooves 11a and the grooves 11b are formed separately by using different masks and the grooves 11b can have a sufficient depth, such as the one reaching the SiO2 layer 11B. However, there arises a problem, in such a process of forming the device isolation grooves 11a and the grooves 11b forming the alignment mark by using separate masks, in that the positioning accuracy at the time of forming the gate electrode pattern on the device region 11a is inevitably deteriorated because of the need of alignment of these different masks.